LNA with Programmable Linearity

ABSTRACT

A receiver front end capable of receiving and processing intraband non-contiguous carrier aggregate (CA) signals using multiple low noise amplifiers (LNAs) is disclosed herein. A cascode having a “common source” input stage and a “common gate” output stage can be turned on or off using the gate of the output stage. A first switch is provided that allows a connection to be either established or broken between the source terminal of the input stage of each cascode. Further switches used for switching degeneration inductors, gate/sources caps and gate to ground caps for each legs can be used to further improve the matching performance of the invention.

BACKGROUND (1) Technical Field

Various embodiments described herein relate to amplifiers, and moreparticularly, to low-noise amplifiers for use in communicationsequipment.

(2) Background

The front-end of a communications receiver typically includes anamplifier, such as a low-noise amplifier (“LNA”). The LNA is responsiblefor providing the first-stage amplification to a signal received by thecommunications receiver. The operational specifications of the LNA arevery important to the overall quality of the communications receiver.Any noise or distortion introduced by the LNA will cause a degradationin the overall receiver performance. That is, the sensitivity of areceiver is in large part determined by the quality of the front-end,and in particular, by the quality of the LNA. The sensitivity of thereceiver, in turn, determines the amount of information that can betransmitted in a predetermined amount of time (e.g., the bit rate inbits per second) at a predetermined bit error rate.

The quality of an LNA is often times characterized by parameters such asthe gain, linearity (i.e., third-order intercept point (IP3) and the 1dB compression point (P1 dB)), noise figure (NF), input impedance match,output impedance match, and the power consumption (i.e., supply voltageand current). These characteristics indicate the amount of distortionlikely to be imposed on signals received through the front-end, howstrong a signal needs to be and the signal-to-interference-plus-noiseratio (SINR) required to recover information transmitted at a particulardata rate. Demand continues to grow for ever higher data rates. Highdata rates require greater accuracy in the demodulation of signalsreceived by today's receivers. Limitations on the amount of gain thatcan be applied without imposition of excessive distortion by thefront-end of the receiver can limit the data rate at which informationmodulated on a signal can be accurately demodulated from the signal oncereceived.

In the case of receivers used in wireless communications, such asreceivers within cellular telephones, the receiver front-end must alsobe capable of handling a wide range of input signal levels. Accordingly,state of the art LNAs must have programmable gain, current andlinearity. In addition, they must maintain good input and outputimpedance matching for maximum power transfer with minimum distortionand a low noise figure when the LNA operates at different bias currentlevels and gain modes.

FIG. 1 shows a simplified illustration of one such state of the artradio frequency (RF) receiver front end 100 having a one-stage cascodecommon-source LNA 102. Typically, such a state of the art LNA isdesigned for the “high gain” and “high bias current” mode of operation.Accordingly, the input/output impedance is matched for the high-gain andhigh-bias-current mode. For lower gain and bias current modes, thecurrent is simply reduced. In addition to reducing the bias current,output and/or input attenuators are used to further reduce the gain.

In the case of RF front-ends for high-end mobile phones, manufacturersrequire that the LNA operate in different gain and current modes withspecified linearity and noise figure. In particular, some manufacturersrequire the LNA to operate in four gain modes: 21 dB, 18 dB, 12 dB and 0dB. These gain modes typically have bias currents of 10 mA, 8 mA, 6 mA,and 2 mA, respectively. The noise figure requirement for each mode maybe 1 dB, 1.2 dB, 3.4 dB and 11.4 dB, respectively. In addition, thelinearity for each mode may be specified in terms of an inputthird-order intercept (IIP3) of −8 dBm, −8 dBm, −6 dBm and 10.5 dBm,respectively.

In the RF front-end 100 shown in FIG. 1, an RF input signal is coupledto the front-end 100 through an input attenuator module 104. The inputattenuator module 104 may be a variable impedance attenuator 106, suchas a continuously-variable attenuator or a step attenuator. The inputattenuator module 104 typically comprises a bypass switch 108.Accordingly, the input signal can be applied directly to the input of animpedance matching and bias network without attenuation. The impedancematching and bias network 110 comprises an input matching inductor 112,a dc-blocking capacitor 114, a bias resistor 116, a variable biasvoltage source 118 and a bypass capacitor 120.

The RF input signal is then coupled to the input of the LNA 102 (i.e.,the gate of a first field effect transistor (FET) 122 within the LNA102). A degeneration inductor 124 is coupled to the source of the FET122. The drain of the FET 122 is coupled to the source of a second FET126. The gate of the second FET 126 is coupled to a variable biasvoltage source 128 and a bypass capacitor 130. The drain of the secondFET 126 is coupled to a load inductor 132, an output impedance matchingnetwork 134 and a bypass capacitor 135. An output attenuator module 136comprising a variable attenuator 138, such as a continuously-variableattenuator or a step attenuator, and a bypass switch 139 couples theoutput signal to the RF front-end output port 140.

The gain of the LNA 102 can be controlled by adjusting a combination ofthe resistance imposed by the input attenuator module 108, theresistance imposed by the output attenuator module 136, the bias voltageapplied to the gate of the first FET 122 and the bias voltage applied tothe gate of the second FET 126. That is, by reducing the bias current ineach of the FETs 122, 126 of the LNA 102 and adding attenuation to theinput and output of the LNA 102, the gain of the RF front end 100 isreduced. However, there are several disadvantages to reducing the gainin this manner.

First, reducing the bias current to force the LNA 102 to operate atlower gain degrades the linearity of the LNA 102. In addition, operatingat lower LNA bias current severely degrades the input impedancematching, causing gain, linearity and noise figure degradation. Addingattenuation to the output assists in reducing the gain, but does notresult in any improvement in the linearity of the LNA 102. The inputattenuator, on the other hand, does improve the impedance match at theinput and the linearity for low gain and high noise figure modes ofoperation. However, the resulting degradation in the noise figure makesit difficult to increase the input impedance for some gain modes, makingit impractical in modes that require a low noise figure.

Furthermore, using attenuator modules requires a relatively large areain the physical layout of an RF front-end 100. In addition, attenuatormodules tend to add parasitic capacitance at the input and output,resulting in degradation in the input and output matching, which resultsin distortion and makes the LNA 102 less efficient. Because the gainrange may be as great as 24 dB, a large number of input and outputattenuators are required. This complicates the design and, as notedabove, significantly increases the die area required to fabricate theLNA 102.

Lastly, in low gain modes, the reduction in the bias current can lead tothe LNA 102 moving out of the saturation region. When this happens,there is a significant degradation in the linearity of the LNA 102.

Therefore, there is currently a need for an RF receiver front-end thatcan operate in several gain, linearity, and/or bias current modes whilemaintaining reasonable noise figure, and with relatively little changeto the input and output impedance.

SUMMARY OF THE INVENTION

A receiver front-end is disclosed that is capable of receiving RF inputsignals having a broad range of signal levels and operating in a varietyof gain and current modes that cover a large gain range. The receiverfront-end comprises an amplifier, such as a low-noise amplifier (LNA).The receiver operates in a plurality of gain and current modes. Thereceiver operates at a low noise figure, high third-order interceptpoint (IP3), and with little difference in the input and outputimpedance of the front-end over the range of gain and current modes. Inaccordance with some embodiments of the disclosed method and apparatus,the LNA maintains a relatively constant current density through the FETsof the amplifier in all gain modes. In order to maintain the samecurrent density, the LNA's Common-Source amplifier (also known asdriver) and Common-Gate amplifier (also known as cascode) are split intoa plurality of amplifier branches, each having a “binary-weight”. Insome embodiments, the binary weight is a function of FET width. As aresult, each branch of the LNA carries a current that is proportional toa binary value. Accordingly, each branch will have a gain having abinary-weight. This allows branches to be turned on in variouscombinations to allow selection of a total bias current across the LNAwithout changing the bias current of any particular branch (other thanto turn the branch on or off).

In some embodiments, a bank of input capacitors can be switched incooperation with the selection of the amplifier branches (i.e.,selection of the gain mode) to ensure that the reactance at the input ofthe LNA (i.e., the imaginary part of the input impedance) is the same ineach gain mode. When selected, the input capacitors are placed betweenthe gate and source of the driver FETs of the LNA.

Furthermore, in some embodiments, a second bank of input capacitors canbe switched in cooperation with the selection of the amplifier branchesto ensure that the impedance at the input of the LNA is the same foreach gain mode.

Still further, in some embodiments, a selectable bank of “gain control”resistive elements can be placed in parallel with a load inductor tofurther reduce the gain of the LNA. In some embodiments, changes to theoutput impedance resulting from adding or subtracting the gain controlresistive elements can be offset by adding or subtracting capacitance inparallel with an output impedance matching capacitor using a selectablebank of gain control compensation capacitors.

Still further, in some embodiments, a bank of output capacitors can beselected in cooperation with the selection of the amplifier branches(i.e., selection of the gain mode). Selection of the output capacitorsensures that the capacitive reactance at the output of the LNA is thesame in each gain mode. When selected, the output capacitors are placedin parallel with the load inductor.

Lastly, in some embodiments, a post fabrication variable gate to sourcecapacitance is provided to allow measurements of parameters of interestregarding the LNA to be made based on post fabrication tuning of thegate to source capacitance and different bias voltages for the FET ofthe LNA.

The details of one or more embodiments of the disclosed method andapparatus are set forth in the accompanying drawings and the descriptionbelow. Other features, objects, and advantages of the disclosed methodand apparatus will be apparent from the description and drawings, andfrom the claims.

DESCRIPTION OF THE DRAWINGS

FIG. 1 is an illustration of an LNA of a prior art communicationsreceiver.

FIG. 2 is an illustration of an LNA of a communications receiver capableof operating in several gain and current modes.

FIG. 3 illustrates the LNA of FIG. 2, having a bank of input capacitorsthat can be selectively placed between a gate and a source of the commonsource FETs of the amplifier branches of the LNA.

FIG. 4 is an illustration of the LNA of FIG. 3, the LNA additionallyhaving a second bank of input capacitors selectively placed in parallelwith a degeneration inductor.

FIG. 5 is an illustration of the LNA of FIG. 4, additionally havingcompensation provided to ensure that the output impedance of the LNAremains constant in each gain mode.

FIG. 6 is an illustration of the LNA of FIG. 5, additionally having abank of gain control resistors and a bank of gain control compensationcapacitors.

FIG. 7 is an illustration of the LNA of FIG. 6, additionally having abank of post fabrication variable capacitors selectively placed inparallel with the gate to source capacitance C_(GS) of the three commonsource amplifiers

FIG. 8 is a flowchart of a process used to make an LNA having capacitorstuned to values that account for variations in the parameters ofcomponents of the LNA during fabrication of the LNA.

Like reference numbers and designations in the various drawings indicatelike elements.

DETAILED DESCRIPTION OF THE INVENTION

FIG. 2 is an illustration of an LNA 200 of one example of acommunications receiver capable of operating in several gain modes. TheLNA 200 comprises a plurality of amplifier branches 202, 204, 206, eachbranch having an amplifier. The inputs to each of the amplifier branchesare coupled together. In some embodiments, a first FET 210 is configuredas a common-source amplifier (i.e., “driver”) and a second FET 208 isconfigured as a common-gate amplifier (i.e., “cascode”). Alternatively,each amplifier branch can be configured as a single common source deviceor a stack of FET devices. In some embodiments, the branches includecombinations of the above configurations. For the sake of simplicity, acascode LNA is described in more detail below. However, it should beunderstood that the following description applies equally to otherconfigurations of amplifier branches.

In some embodiments, each branch 202, 204, 206 has a “binary-weight” β.Accordingly, in some such embodiments, the width of the FETs 208, 210 ineach branch 202, 204, 206 is proportional to the binary weight β of thatbranch. Accordingly, in some such embodiments, the gain of each branchis also proportional to β (i.e., each branch has a binary-weightedgain). In other embodiments, the relative weight of the branches may bedistributed differently, such as in a thermometer weighting, geometricor logarithmic weighting, arbitrary weighting or other weighting scheme.

In the case of a binary weighting scheme, the binary weight β of eachbranch is 2^(i-1)/(2^((n))−1), where i is the branch number from 1 to n,and n is the total number of branches. In this example, the LNA 200comprises a total of three branches 202, 204, 206. Therefore, the valueof n is 3. The value of i for the first branch is 1. Therefore, theweight β of the first branch is 2⁰/(2 ⁽³⁾−1)= 1/7. The value of i forthe second branch is 2, thus the weight β of the second branch is2¹/(2⁽³⁾−1))= 2/7. The value of i for the third branch is 3, thus theweight β of the third branch is 2²/(2⁽³⁾−1)= 4/7. The number of brancheswill depend upon the granularity of weighting steps desired, as will beclear from the following description. In some embodiments, the gain ofeach branch 202, 204, 206 is proportional to the weight β of thatbranch. In other embodiments, other parameters, such as current, noisecontribution, delivered output power, linearity level, etc. could be theprimary metric that is weighted.

In some embodiments, the gain of each branch is set by establishing thewidth of the two FETs 208, 210 proportional to β. That is, the width ofthe FET 210 of the first branch is 1/7^(th) the width of the amplifierFET that would be needed to achieve the same gain in a conventional LNAthat has just one such driver FET (i.e., one branch). Similarly, thewidth of the FET 208 of the first branch is 1/7^(th) the width of acascode amplifier FET that would be needed to achieve the same gain in aconventional LNA having just one such cascode FET.

The width of the FET 210 of the second branch is 2/7^(th) the width ofthe driver amplifier FET that would needed to achieve the same gain in aconventional LNA. It should be clear that the width of each other FET208, 210 is proportional to the binary weight β of the branch in whichthe FET 208, 210 resides.

A pair of branch control switches 212, 214 associated with the firstbranch 202 controls the bias to the gate of the cascode FET 208 of thatbranch. A branch 1 switch control signal coupled to the switch 212controls when the switch is to be opened and closed. For the sake ofsimplicity, only the switch 212 is shown having a branch switch controlsignals coupled thereto. However, each of the other branch controlswitches 214, 220, 222, 224, 226 is controlled by a corresponding switchcontrol signal.

By opening the switch 212 to a bias voltage source 216 and closing theswitch 214 to ground, the bias is removed from the gate of a cascode FET208. Accordingly, the drain current I_(d) flowing through the branch isturned off, essentially removing that branch from operation and reducingthe gain contribution of that branch to the overall gain of the LNA 200to zero. Similarly, pair of switches 220, 222, 224, 226 associated withthe other two branches, respectively, turns those branches on and off.In some embodiments, a gain control module produces branch switchcontrol signals that are coupled to switches 212, 214, 220, 222, 224,226 to allow the gain control module to turn each branch on or off,depending upon the amount of gain desired. The LNA can thus be operatedin steps of 1/7^(th) the maximum gain. That is, with only the firstbranch 202 turned on, the LNA 200 will operate at 1/7^(th) maximum gain.With only the second branch turned on, the LNA 200 will operate at2/7^(th) maximum gain. With both the first and the second branch turnedon, the LNA 200 will operate at 3/7^(th) maximum. With only the thirdbranch turned on, the LNA 200 will operate at 4/7^(th) maximum gain,etc.

Splitting the LNA 200 into several branches allows the bias currentthrough each FET 208, 210 to remain constant at a bias current level atwhich the branch was designed to operate.

When a branch 202, 204, 206 is turned OFF, its common-gate amplifierformed by the cascode (FET 208 for branch 202, for example) is turnedOFF by grounding its gate. Thus, the FET 208 does not draw current.However, in some embodiments, the common-source amplifier formed by thecascode FET 210 is not OFF. Rather, that FET 210 is in “triode” mode, asits gate is still biased. Therefore, as the different branches areturned on and off, the input impedance of the LNA 200 may change. Asnoted above, this is undesirable. This is mitigated in some embodiments,in which the input impedance of the LNA 200 is maintained constant fordifferent gain modes (i.e., with different combinations of branchesbeing turned on).

FIG. 3 is an illustration of one embodiment of an LNA 300 similar to theLNA 200 shown in FIG. 2. However, the LNA 300 shown in FIG. 3 comprisesa bank of selectable gate-to-source compensation capacitors (GSC Caps)302, 304, 306. Each GSC Cap 302, 304, 306 corresponds with one of thebranches 202, 204, 206 of the LNA 200. Each GSC Cap 302, 304, 306 iscoupled to a GSC Cap switch 308, 310, 312 to allow the GSC 302, 304, 306Cap to be selected. The gate to source capacitance C_(gs) within a FETchanges depending on whether the FET is in the saturation mode or triodemode, thereby changing the input impedance of the LNA 300. In someembodiments, the capacitance of each of the GSC Caps 302, 304, 306 isset equal to the difference between the C_(gs) of the FET 210 insaturation and the C_(gs) of the FET 210 in triode mode. Combinations ofthe GCS Caps 302, 304, 306 are thus selected to mitigate changes in theinput impedance in each of the possible gain modes. That is, theresulting change in the input reactance of the LNA 300 due to the changeof the C_(gs) of FETs 210 from saturation mode to triode mode can bemitigated (and essentially eliminated) by closing the GSC Cap switch308, 310, 312 associated with those branches that are turned off.

In some embodiments, each of the GSC Cap switches 308, 310, 312 arecontrolled by the gain control module 218, such that the GSC Cap switch308, 310, 312 coupled to the GSC Cap 302, 304, 306 is closed when thecorresponding branch 202, 204, 206 of the LNA 200 is turned off. The GSCCap switch is then opened when the corresponding branch is turned on.Adding capacitance between the gate and the source of the driver FETs202, 204, 206 of the LNA 300 compensates for the difference between theinput impedance in each of the different operational modes.

FIG. 4 illustrates an LNA 400 having a bank of degeneration capacitors402, 404, 406. Similar to the first bank of capacitors 302, 304, 306,the bank of degeneration capacitors 402, 404, 406 are switched in andout of the circuit in coordination with the selection of the gain modeof the LNA 400. In some embodiments, the switching is controlled by again control module 218 as disclosed above. By closing the associatedswitches 408, 410, 412 one or more of the capacitors 402, 404, 406 areplaced in parallel with the degeneration inductor 414. By changing theamount of capacitance in parallel with the degeneration inductor 414 asthe LNA 400 changes gain modes, the total input impedance that is seenlooking into the input of the LNA 400 can be adjusted so that the inputimpedance remains essentially constant for each gain mode. Accordingly,the degeneration capacitors 402, 404, 406 are tuned to keep the inputimpedance the same in each of the possible gain modes. Note that a firstof the three switches 408 is associated with the switches 214, 220associated with the first branch 202, as well as with a first of thethree switches 308. Therefore, when the first branch is turned on,switches 308, 408 are opened. Likewise, when the second branch 204 isturned on, the switches 310, 410 are opened. Finally, when the thirdbranch 206 is turned on, the switches 312, 412 are opened.

FIG. 5 is an illustration of yet another embodiment of an LNA 500 inwhich compensation is provided to ensure that the output impedance ofthe LNA 500 remains constant in each gain mode. The LNA 500 has a loadinductor 514 coupled between a voltage supply VDD and the drains of thecommon-gate FETs 208. The compensation for changes that would otherwiseoccur in the output impedance is provided by a third bank of outputimpedance compensation (OIC) capacitors 502, 504, 506 that can each beplaced in parallel with the load inductor 514 by closing an associatedswitch 508, 510, 512. That is, when a branch 202, 204, 206 of the LNA isturned off, the output impedance decreases. This results in an outputimpedance mismatch. By providing additional capacitor in parallel withthe load impedance 514 when a branch is turned off, the mismatch can beimproved. Accordingly, each of the three switches 508, 510, 512 areassociated with one of the three branches 202, 204, 206. When a branch202, 204, 206 is turned off, the associated switch 508, 510, 512 isclosed. As was the case in the LNAs 400, 300 discussed above, a gaincontrol module 218 (not shown in FIG. 5 to simplify the figure) can beprovided to control and coordinate the operation of the branches 202,204, 206 and the switches.

FIG. 6 is an illustration of yet another embodiment of an LNA 600 havinga bank of gain control resistors 602, 604, 606. Each of the gain controlresistor 602, 604, 606 is associated with a gain control switch 608,610, 612 that places the associated gain control resistor 602, 604, 606in parallel with the load inductor 514. By closing the switch 608, 610,612 associated with each of the gain control resistors 602, 604, 606,the gain of the LNA 600 can be reduced, providing additional controlover the gain of the LNA 600. Unlike the switches 408, 410, 412, 508,510, 512 that are each associated with one of the branches 202, 204,206, the gain control switches 608, 610, 612 can be operatedindependently to provide additional gain modes. However, the same gaincontrol module 218 used to turn the branches on and off can provideadditional control outputs that open and close the switches 608, 610,612. Adding additional gain control resistor in parallel with the loadinductor 514 will change the output impedance of the LNA 600.Accordingly, in some embodiments, an additional degree of freedom toalter the output impedance is provided by a bank of gain controlcompensation capacitors 616, 618, 620, each associated with a switch622, 624, 626 that can place the associated capacitor in parallel withan output capacitor 628. The gain control compensation capacitors 616,618, 620 are tuned to have values that will mitigate changes to theoutput impedance that would otherwise occur for each combination of gaincontrol switches being opened or closed. Providing the gain controlcompensation capacitors 616, 618, 620 makes it possible to keep theoutput impedance essentially the same when different combinations ofgain control resistors 602, 604, 606 are placed to be in parallel withthe load inductor 514.

FIG. 7 is an illustration of one more embodiment of an LNA 700 in whicha bank of variable capacitors 702, 704, 706 are selectively placed inparallel with the gate to source capacitance C_(GS) of the three commonsource amplifiers, such as FETs 210. In some embodiments, the capacitors702, 704, 706 are “post fabrication variable”. That is, the amount ofcapacitance can be adjusted after fabrication of the other components ofthe amplifier branch 202, 204, 206. By making the value of thesecapacitors 702, 704, 706 variable, variations during fabrication thatcan affect parameters of interest of the LNA 700 (such as the IIP3,noise figure, input second order intercept (IIP2), output impedance,input impedance, etc.) can be compensated for after fabrication iscomplete. In some embodiments, the capacitors 702, 704, 706 are eachMetal-Insulator-Metal (MIM) caps that can be laser trimmed to thedesired capacitance after the LNA 700 has been fabricated.Alternatively, additional capacitors and associated switches can beprovided to increase the range of capacitance that can be varied afterfabrication with selectively coupling the additional capacitors throughthe additional switches. The capacitors 702, 704, 706 are shown in FIG.7 as three variable capacitors. However, in some embodiments, eachcapacitor 702, 704, 706 may comprise a fixed capacitor in parallel with(or in series with) a MIM capacitor that can be laser trimmed to yieldthe desired total capacitance for each capacitor 702, 704, 706 shown orseveral additional capacitors and associated switches. In addition, thebias voltages V_(bias1), V_(bias2) and V_(bias3) applied to the gate ofeach of the three common gate amplifiers (such as FETs 208) are eachgenerated using variable voltage sources 708, 710, 712.

Throughout this disclosure, the terms “resistor”, “capacitor” and“inductor” have been used in the general sense to indicate an elementthat imposes resistance, capacitance and inductance, respectively. Itshould be understood that these terms can be interpreted to mean anyelement, either lumped or distributed, that can impose resistance,capacitance and inductance, respectively. Likewise, the term “switch”has been used through the disclosure to mean any circuit element thatcan selectively impose either a relatively high impedance in a firststate and a relatively low impedance in a second state. In someembodiments, these switches are FETs. However, any other element capableof switching from a relatively high impedance to a relatively lowimpedance can be used where practical.

FIG. 8 is a flowchart of a process used to make an LNA 700 havingcapacitors 702, 704, 706 tuned to values that account for variations inthe parameters of components of the LNA during fabrication of the LNA700. The process begins with the fabrication of LNAs 700 includingcapacitors 702, 704, 706 that can be adjusted, such as by laser trimminga MIM capacitor, after fabrication (STEP 802). Once the LNAs 700 havebeen fabricated, at least one of the LNAs 700 is selected. For theselected LNA 700, initial values are set for capacitance for the threecapacitors 702, 704, 706 and for the common gate (CG) bias voltageV_(bias1), V_(bias2) and V_(bias3) applied to each of the common gateFETs 208 and for the common source (CS) bias voltage V_(bias4) appliedto the common source FETs 210 (STEP 804).

Next, at least one LNA parameter of interest, such as the IIP3, noisefigure, input second order intercept (IIP2), output impedance, inputimpedance, etc., are measured at the initial values of CG bias and CSbias for a first gain mode in which the first branch 202 is turned onand each of the other branches 204, 206 are turned off (STEP 806). Ifmeasurements have not been made at all of the CG bias voltages for whichmeasurements are to be made (STEP 808), then the CG bias voltage for thebranch that is currently turned on is adjusted to the next value (STEP810). The parameters of interest are measured for that CG bias voltage(STEP 806). STEPs 806, 808 and 810 are repeated until the answer to thedecision block in STEP 808 is “YES” (i.e., parameter measurements forall of the bias voltage levels have been made).

Upon making measurements of the parameters of interest at each CG biasvoltage level, a decision is made as to whether parameter measurementshave been made for all of the CS bias voltage values (STEP 812). If not,then the CS bias voltage is set to the next level at which parametermeasurements are to be made (STEP 814). The next measurement is made(STEP 806) and the process again repeats STEP 806 through STEP 814 untilthe answer to the decision block in STEP 812 is “YES”.

Once the answer to the decision block in STEP 812 is “YES”, adetermination is made as to whether parameter measurements for all ofthe branches 202, 204, 206 have been completed. If not, then the nextbranch is turned on and each of the other branches is turned off (STEP818). Once the answer to the decision block in STEP 816 is “YES”, theparameter measurements are analyzed to determine the CS bias voltage andCG bias voltage that results in desired operational parameters of thecomponents of the LNA 700 (STEP 820).

The process performed in STEPs 802 through 820 are repeated for otherLNAs 700 from the same fabrication lot (i.e., that were fabricatedtogether and thus have the same operational characteristics), but withdifferent values of capacitance for the capacitors 702, 704, 706. Thisprocess is repeated until parameters of interest for LNAs 700 having alldesired values of capacitance for the post fabrication variablecapacitors 702, 704, 706 have been measured (STEP 822). The parametermeasurements are then analyzed to determine the amount of capacitance(e.g., the size) of the variable capacitors 702, 704, 706 necessary tocompensate for any variations from the ideal operational parameters ofthe LNA 700. The value of each of the variable capacitors 702, 704, 706for the remaining LNAs of the lot are then set (STEP 824). In someembodiments, the capacitors 702, 704, 706 are MIM capacitors that can belaser trimmed, as noted above. Therefore, the values are set by lasertrimming each capacitor to the appropriate size indicated by theparameter measurements made in STEP 806.

In some embodiments, the process of FIG. 8 is performed on samples takenfrom a lot of LNAs that were fabricated together (i.e., LNAs for whichthe components all have the same performance parameters). The MIMcapacitor of each of the samples can be trimmed to different values andthe process of FIG. 8 performed on each sample to determine which samplehas the most desirable parameters of interest. In some embodiments, theMIM capacitor 702, 704, 706 of a first sample can be trimmed to a sizethat provides values of 20% of the impedance resulting from C_(gs) ofthe common source FET 210. Other samples can have the capacitors 702,704, 706 trimmed to other values, such as 30%, 40% or 0% of C_(gs). Oncethe measurements of STEP 806 are all completed for each sample, thesample having the best operational characteristics can be used as amodel for determining the size of the capacitors 702, 704, 706. In someembodiments, the MIM capacitors of the remaining LNAs 700 that werefabricated together with the samples that were measured are trimmed tothe same value as the LNA 700 having the best measurements for theparticular application for which the LNA 700 is to be used.Alternatively, a new LNA 700 can be designed based on the measurementsmade on the samples and the process repeated using the new design andtaking samples from the resulting LNAs 700.

Fabrication Technologies and Options

As should be readily apparent to one of ordinary skill in the art,various embodiments of the disclosed apparatus can be implemented tomeet a wide variety of specifications. Unless otherwise noted above,selection of suitable component values is a matter of design choice andvarious embodiments of the claimed invention may be implemented in anysuitable IC technology (including but not limited to MOSFET and IGFETstructures), or in hybrid or discrete circuit forms. Integrated circuitembodiments may be fabricated using any suitable substrates andprocesses, including but not limited to standard bulk silicon,silicon-on-insulator (SOI), silicon-on-sapphire (SOS), GaN HEMT, GaAspHEMT, and MESFET technologies. However, in some cases, the conceptsclaimed may be particularly useful with an SOI-based fabrication process(including SOS), and with fabrication processes having similarcharacteristics.

A number of embodiments of the claimed invention have been described. Itis to be understood that various modifications may be made withoutdeparting from the spirit and scope of the claimed invention. Forexample, some of the steps described above may be order independent, andthus can be performed in an order different from that described.Further, some of the steps described above may be optional. Variousactivities described with respect to the methods identified above can beexecuted in repetitive, serial, or parallel fashion. It is to beunderstood that the foregoing description is intended to illustrate andnot to limit the scope of the claimed invention, which is defined by thescope of the following claims, and that other embodiments are within thescope of the claims.

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 20. Anamplifier comprising: (a) a plurality of amplifier branches at least onewhich includes a plurality of FETs; (b) a plurality of branch controlswitches, each branch control switch coupled to a correspondingamplifier branch; (c) a load inductance coupled between a drain of acommon-gate amplifier and a voltage supply and a plurality of gaincontrol resistors selectively placed in parallel with the loadinductance; and (d) a plurality of gain control compensation switches,each gain control compensation switch corresponding to one of aplurality of gain control compensation capacitors and coupled to thecorresponding gain control compensation capacitor to place thecorresponding gain control compensation capacitor in parallel with anoutput capacitor when the corresponding gain control compensation switchis closed.
 21. The amplifier of claim 20, wherein the output capacitoris coupled between the drain of the common-gate amplifier and an RFoutput.
 22. The amplifier of claim 21, further comprising a plurality ofgain control switches, each gain control switch associated with acorresponding one of the gain control resistors to place the associatedgain control resistor in parallel with the load inductor to select acorresponding gain mode when the associated gain control switch isclosed.
 23. The amplifier of claim 22, wherein the amplifier has anoutput impedance, wherein closing unique combinations of gain controlswitches corresponds to unique gain modes and wherein combinations ofthe gain control compensation capacitors are tuned to mitigate changesbetween the output impedance in each of the possible gain modes. 24.(canceled)
 25. (canceled)
 26. (canceled)
 27. (canceled)
 28. (canceled)29. Method for fabricating and tuning a low noise amplifier (LNA), themethod comprising: (a) fabricating a plurality of LNAs, each LNA havingat least one amplifier branch, the at least one amplifier branch havingat least a common gate amplifier, a common source amplifier and a postfabrication variable capacitor in parallel with the gate to sourcecapacitance of the common source amplifier; (b) for a first LNA of theplurality of LNAs, adjusting the capacitance of each of the postfabrication variable capacitors to a first capacitance value; (c)applying an initial CS bias voltage to the common source amplifier ofthe first of the at least one amplifier branches of a first of theplurality of LNAs; (d) applying an initial CG bias voltage to the commongate amplifier of a first of the at least one amplifier branches to turnthe first amplifier branch; (e) measuring LNA parameters of interest;(f) adjusting the CG bias voltage; (g) repeating steps (d) and (e) untilmeasurements at all desired CG bias voltage values have been made; (h)adjusting the CS bias voltage; (i) measuring LNA parameters of interest;(j) repeating steps (c) through (h) until measurements at all desired CSbias voltage values have been made; (k) repeating steps (c) through (i)for each of the remaining at least one amplifier branches; (l) comparingthe measurements to determine a desired CG bias voltage and CS biasvoltage; (m) for a next LNA from among the plurality of LNAs, adjustingthe capacitance of each of the post fabrication variable capacitors to anext capacitance value; (n) repeating (c) through (m) until parametersof interest for LNAs having all desired values of capacitance for thepost fabrication variable capacitors have been measured; (o) determiningthe desired values of capacitance for the post fabrication variablecapacitors based on the measurements of the parameters of interest; and(p) adjusting the capacitance of the post fabrication variablecapacitors of each of the remaining LNAs to the value determined in (o).30. The method of claim 29, further comprising fabricating additionalLNAs, each of the additional LNAs having at least one amplifier branch,the at least one amplifier branch having at least a common gateamplifier, a common source amplifier and a post fabrication variablecapacitor in parallel with the gate to source capacitance of the commonsource amplifier, wherein the characteristics of the post fabricationvariable capacitor are determined based on the measurements made on thepreviously fabricated LNAs.
 31. The method of claim 30, furthercomprising repeating (b) through (p) of claim 29 for the additionalLNAs.